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1 low power audio adc features system ? high performance and low power multi - bit delta - sigma audio adc ? i 2 s/pcm master or slave serial data port ? two pair s of analog input with differential input option ? 256 /384fs and u sb 12/ 24 mhz system clocks ? fast power up time ? i 2 c interface adc ? 24- bit, 8 to 96 khz sampling frequency ? 9 6 db signal to noise ratio, - 85 db thd+n ? low noise pre - amplifier ? auto level control (alc) and noise gate ? high psrr ? shelving filter to compensate mic frequency response ? support digital mic low power ? 1.8v to 3.3v operation ? 9 mw record ? low standby current a pplications ? wireless remote ? portable audio o rdering i nformation ES8218E -40 c ~ +85 c qfn -2 0 ES8218E
everest semiconductor confidential ES8218E revision 9 .0 2 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 1. block diagram dvdd pvdd dgnd avdd agnd adcvref vmid mclk cdata cclk ce asdout sclk lrck lin2 lin1 rin1 rin2 i 2 c pga power supply i 2 s/pcm adc alc mono adc analog reference pga clock mgr
everest semiconductor confidential ES8218E revision 9 .0 3 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 2. pin out and description pin name i/o description 1 cclk i i 2 c clock input 2 mclk i master clock 3 dvdd supply digital core supply 4 p vdd supply digital io supply 5 dgnd supply digital ground 6 s clk i/o audio data bit clock 7 lrck i/o audio data left and right clock 8 asdo ut o adc audio data 9 dmic_ s cl digital mic clock 10 avdd supply analog supply 11 agnd supply analog ground 12 adc vref o d ecoupling capacitor 13 vmid o d ecoupling capacitor 14 rin 2 i right analog input 15 lin 2 i left analog input 16 rin1 i right analog input 17 lin1 i left analog input 18 micbias mic bias 19 c e i i 2 c d evice address selection 20 cdata i/o i 2 c data input or output ES8218E cclk mclk dvdd pvdd dgnd 1 2 3 4 5 lin2 rin2 vmid adcvref agnd 15 14 13 12 11 rin1 lin1 micbias ce cdata 16 17 18 19 20 avdd dmic_scl asdout lrck sclk 10 9 8 7 6
everest semiconductor confidential ES8218E revision 9 .0 4 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 3. typical application circuit va 0.1uf 0.1uf 1uf vd vp agnd agnd mcu/ dsp 1uf 1uf 1 2 dmi c1 cc lk 1 m c lk 2 p vd d 4 dgnd 5 lrc k 7 asdout 8 dmi c_sc l 9 avdd 10 vmid 13 adcvref 12 agnd 11 lin 1 17 mi cb ias 18 ce 19 cd ata 20 dvdd 3 ri n2 14 lin 2 15 ri n1 16 sclk 6 pgnd 21 ES8218E agnd for the best performance,decoupling and filtering capacitors should be located as close to the device package as possible additional parallel capacitors(typically 0.1 f) can be used, larger value capacitors (typically 10 f) would also help 1uf agnd * 1uf * * * mic2p mic2n 1uf agnd 1uf agnd * * agnd 0r gnd(sys) in the layout, chip is treated as an analog device
everest semiconductor confidential ES8218E revision 9 .0 5 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 4. clock modes and samp ling frequencies the device supports two types of clocking: standard audio clocks (256fs, 384fs, 512fs, etc), and usb clocks (12/24 mhz) . according to the serial audio data sampling frequency (fs), the device can work in two speed modes: single speed mode or double speed mode. in single speed mode, fs normally ranges from 8 khz to 48 khz, and in double speed mode, fs normally range from 64 khz to 96 khz. the device can work either in master clock mode or slave clock mode. in slave mode, lrck and sclk are supplied externally, and lrck and sclk must be synchronously derived from the system clock with specific rates. in master mode, lrck and sclk are derived internally from device master clock. 5. micro - controller configura tion i nterface the device supports standard i 2 c micro - controller configuration interface. external micro - controller can completely configure the device through writing to internal configuration registers. i 2 c interface is a bi - directional serial bus that uses a serial data line (sda) and a serial clock line (scl) for data transfer. the timing diagram for data transfer of this interface is given in figure 1. data are transmitted synchronously to scl clock on the sda line on a byte - by - byte basis. each bit in a byte is sampled during scl high with msb bit being transmitted firstly. each transferred byte is followed by an acknowledge bit from receiver to pull the sda low. the transfer rate of this interface can be up to 4 00 kbps. figure 1 data transfer for i 2 c inter face a master controller initiates the transmission by sending a start signal, which is defined as a high - to - low transition at sda while scl is high. the first byte transferred is the slave address. it is a seven - bit chip address followed by a rw bit. th e chip address must be 001000x, where x equals ad0. the rw bit indicates the slave data transfer direction. once an acknowledge bit is received, the data transfer starts to proceed on a byte - by - byte basis in the direction specified by the rw bit. the maste r can terminate the communication by generating a stop signal, which is defined as a low -to - high transition at sda while scl is high.
everest semiconductor confidential ES8218E revision 9 .0 6 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com in i 2 c interface mode, the registers can be written and read. the formats of write and read instructions are shown i n table 1 and table 2 . please note that, to read data from a register, you must set r/w bit to 0 to access the register address and then set r/w to 1 to read data from the register. table 1 write data to register in i 2 c interface mode chip address r/w reg ister address data to be written 001000 ad0 0 ack ram ack data table 2 read data from register in i 2 c interface mode chip address r/w register address 001000 ad0 0 ack ram chip address r/w data to be read 001000 ad0 1 ack data 6. digital audio interface the device provides many formats of serial audio data interface to the output from the adc through lrck, bclk (sclk) and adcdat pins. these formats are i 2 s, left justified and dsp/pcm mode. adc data is out at adcdat on the falling edge of sclk. t he relationships of sdata (adcdat), sclk and lrck with these formats are shown through figure 2 to figure 6. n-2 n-1 n 3 2 1 1 n-2 n-1 n 3 2 1 1 figure 2 i 2 s serial audio data format up to 24 - bit n-2 n-1 n 3 2 1 n-2 n-1 n 3 2 1 figure 3 left justified serial audio dat a format up to 24 - bit
everest semiconductor confidential ES8218E revision 9 .0 7 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com figure 5 dsp/pcm mode a figure 6 dsp/pcm mode b
everest semiconductor confidential ES8218E revision 9 .0 8 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 7. electrical character istics absolute maximum rat ings continuous operation at or beyond these conditions may permanently damage the device. parameter min max analog supply voltage level - 0.3v +5.0v digital supply voltage level - 0.3v +5.0v input voltage range dgnd - 0.3v dvdd+0.3v operating temperature range - 40 c +85 c storage temperature -65 c +150 c recommended operatin g conditions parameter min typ max unit analog supply voltage level 1.6 3.3 3.6 v digital supply voltage level 1.6 1.8 3.6 v adc analog and filte r characteristics an d specifications test conditions are as the following unless otherwise specify: avdd=3.3v, dcvdd=1.8v, agnd=0v, dgnd=0v, ambient temperature=25 c, fs=48 khz, 96 khz or 192 khz, mclk/lrck=256. parameter min typ max unit adc performance signal to noise ratio (a - weigh) 90 9 6 9 8 db thd+n - 88 - 85 - 75 db gain error 5 % filter frequency response C single speed passband 0 0.4535 fs stopband 0.5465 fs passband ripple 0.05 db stopband attenuation 50 db filter frequency response C double speed passband 0 0.4167 fs stopband 0.5833 fs passband ripple 0.005 db stopband attenuation 50 db analog input full scale input level avdd/3.3 vrms input impedance 20 k
everest semiconductor confidential ES8218E revision 9 .0 9 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com power consumption ch aracteristics parameter min typ max unit normal operation mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v: dvdd=3.3v, pvdd=3.3v, avdd=3.3v: 9 28 mw power down mode dvdd=1.8v, pvdd=1.8v, avdd=1.8v dvdd=3.3v, pvdd=3.3v, avdd=3.3v 0. 1 0. 1 ua ua serial audio port sw itching specificatio ns parameter symbol min max unit mclk frequency 51.2 mhz mclk duty cycle 40 60 % lrck frequency 200 khz lrck duty cycle 40 60 % sclk frequency 26 mhz sclk pulse width low tsclkl 15 ns sclk pulse width high tsclkh 15 ns sclk falling to lrck edge tslr C 10 10 ns sclk falling to sdout valid tsdo 0 ns sdin valid to sclk rising setup time tsdis 10 ns sclk rising to sdin hold time tsdih 10 ns figure 8 serial audio port timing
everest semiconductor confidential ES8218E revision 9 .0 10 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com i 2 c switching specific ations parameter symbol min max unit scl clock frequency f scl 400 khz bus free time between transmissions t twid 1.3 us start condition hold time t twsth 0.6 us clock low time t twcl 1.3 us clock high time t twch 0.4 us setup time for repeated start condition t twsts 0.6 us sda hold time from scl falling t twdh 900 ns sda setup time to scl rising t twds 100 ns rise time of scl t twr 300 ns fall time scl t twf 300 ns s p sda scl t twsts t twsth t twch t twcl t twdh t twds t twf t twr s t twid figure 10 i 2 c timing
everest semiconductor confidential ES8218E revision 9 .0 11 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 8. package
everest semiconductor confidential ES8218E revision 9 .0 12 september 2018 latest datasheet: www.everest - semi.com or info@everest - semi.com 9. corpo rate information everest semiconductor co., ltd. no. 1355 jinjihu drive, suzhou industrial park , jiangsu, p.r. china , zip code 215021 ????? 1355 ???? , ? 215021 email: info@everest - semi.com

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